"Febuary" Progress Update

I said I'd have another progress update in February, so here it is! I've made great progress on multiple fronts, and run into a few ongoing challenges along the way. For those uninitiated, I'm working on creating emulations of late-70's era discrete video game chips. You can find a more in-depth review in my last update.

Its funny to think how this project, which was originally just reverse-engineering the AY-3-8500, would have been completed months ago had it not been for me moving the goalposts. Here are my current long-term goals:

1. Create a FPGA emulation of the AY-3-8500(-1) for a FPGA system such as MiSTer

2. Make a software-only emulation of the AY-3-8500(-1) in MAME

3. Use the experience/tools gained to repeat the process for as many of the other 2 dozen+ discrete game chips out there

Lets take a look at what's been accomplished over the last month and a half.

FPGA emulation

As explained before, I've been working on creating a program to reverse-synthesize the low-level netlist of the AY-3-8500-1 chip into more abstract components which would be eventually converted into a Verilog circuit description file. This file can be used to configure a FPGA, a chip which contains mesh of re-programmable logic blocks. Current testing is done on a tinyFPGA-BX board, although I'll probably port it to something else (more on that later.)

The 972 nodes which make up the AY-3-8500 were reduced to 360 by the last update, it's now down to 318. That number is not very important, it just shows the reductions that are possible through reverse-synthesis. Those 318 components create a Verilog file which, after one or two manual patches, is programmed into the FPGA board via USB. Connecting the circuitry to a TV give us...

 

Squash, along with a visitor

...a game of "handicap"! Unfortunately it doesn't play or show the scores yet, as explained below. All of the virtual chip's pins have been mapped to the board's pins so attaching a grounded jumper to pin 4 will display a squash game. Grounding pin 5 will result in a tennis game, pin 6 Soccer, etc...

Tennis appearing sharp, albeit less retro on a digital TV

Below is the breadboard setup, on the left is the tinyFPGA board, andnext to it is a reset button. To the right of that is a 2x quad-OR gate, and past that  is a resistor network and controller circuits. The circuitry is almost exactly like the diagram in the manual, just with different value components and a direct composite connection instead of a RF-modulator. I goofed up and ordered a non breadboard-friendly RCA plug, which is why the connector dangles off the board (its connected to the two wires leaving the right side of the picture.)

Nothing a little soldering won't fix

As you can see, the current setup is not at all user-friendly, given it's composite-only output, support circuity, and cat-vulnerable mess of wires. This is because, the FPGA is currently emulating the AY-3-8500 and nothing else. If we ignore the 4 unchangeable pins and the voltage difference, the configured board can be pin-compatible with the original!

I'm planning on porting it to a core for the MiSTer FPGA retrogaming system, once I get a hold of a DE-10 Nano board to test it. This will eliminate the support circuitry and allow for VGA or HDMI output, among other things.

 

 

Challenges

The paddle inputs are currently not working correctly due to either an incorrectly configured pin or because the board is hooked up to wrong value potentiometers. The internal paddle circuitry is working as expected though (I tested this by adding code to trigger the pins based on the vertical counter, which is why the paddles appear above.)

The reason why the score display/playing capabilities don't work yet is due to a more complex problem. Almost all modern digital logic is synchronous, meaning registers only update when the clock signal does. Because signals with different latencies must wait for the synchronized clock, they won't trigger race conditions as long as the clock is no faster than the slowest signal.

The AY-3-8500 uses some more complex asynchronous logic along with "nasty tricks" such as pulse-on-edge circuits and latches which make porting to modern hardware difficult. Note that its difficult but not impossible. Working asynchronous logic can be created, in fact its an area of active research in semiconductor design. The problem is software tools can't handle it's unique needs yet, and the FPGA hardware blocks are built with synchronous logic in mind.

A "nasty" on-edge-pulse circuit

I believe this is possible though. Latches can be made inside FPGAs by combining many logic blocks. This is inefficient on resources, however the FPGA I'm using can already hold multiple copies of the AY-3-8500. Many of the "nasty tricks" can (and have been) eliminated during processing while keeping behavior identical. Lastly the AY-3-8500 only needs to run at a snailish 2Mhz which eliminates some of the problems associated with asynchronous logic.

That doesn't mean there won't be issues. For example, the logic which loads the score shift register is somehow being affected by component placement, despite the fact that it loads synchronously with ample time for signal propagation! This has had me stumped for a while. Hopefully changing the build tools from arachne-pnr to nextpnr will fix or offer insight into this issue. Also, I would like to thank David Shah and Claire Wolf (two of the developers) for taking the time to answer my (possibly bothersome) questions on these issues.

Another challenge: SABOTAGE!

Other Advancements

No software-emulation specific work has been done yet, although I have some good news regarding speed. I simulated the circuitry in a program called Icarus and measured the execution speed at 1/9th real world speed. This would only allow for playable emulation on PCs in the "overclocked i9 with water cooling" range, thankfully there are much faster methods of circuit simulation. Icarus runs by interpreting intermediate files, while Verilator works by converting the source into very high speed C++ code. It claims improvements of 100X, which seem reasonable given the actual work involved (I estimated that 75% of the AY-3-8500 cycles consist of merely incrementing two counters.) Once bugs have been ironed out via FPGA testing, I should be able to Verilator-ify the file and write a driver to interface it to MAME.

What about the other chips? Another one is currently in the process of being highlighted. Its the AY-3-8606-1 "Wipeout" chip which is a weird cross between pong and breakout. Unlike the well-documented AY-3-8500, I've only been able to find one video of it online. So far the transistor and via layers have been completely marked, and the diffusion layer is about 80% complete. Once highlighting is done, I'll pop it into the JavaScript sim for debugging before converting it to Verilog. Then, you know the drill, its onto the FPGA and into MAME.

The diffusion layer, about two-thirds highlighted

Another accomplishment: I contacted one of the engineers who designed the game chips at General Instruments back in the 'day. Unfortunately he doesn't have/know of any surviving design information related to the video game chips developed there. I do have a few questions to ask him sometime regarding the development process and the history behind the circuits, including the advertised but unreleased ones.

That brings me to something that popped up not long ago, an interview with the AY-3-8500's designer! Give a big thanks to Nate Lockhart for interviewing Mr Harrower, and Mr Harrower for agreeing to be interviewed. I'm looking forward to the follow-up on the Intellivision hardware development.

Well, these chips are not going to emulate themselves! It shouldn't be long before I have a JavaScript simulation of the AY-3-8606 and a more complete FPGA emulation of the AY-3-8500. In the meantime if you want see bouncing white squares, check out this impressive re-creation of the AY-3-8500 that Grant Seale made on an Arduino (or standalone micro-controller.)